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Signal integrity and scalability study of a novel PoP inter-package system

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4 Author(s)
Jackson Kong ; Intel Microelectronics (M) Sdn Bhd, Bayan Lepas FIZ, Phase 3, Halaman Kampung Jawa, 11900 Penang, Malaysia ; Bok Eng Cheah ; Shanggar Periaman ; Kooi Chi Ooi

A novel enabling technique exploiting interposer approach such as silicon and package interposer [1] in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution is presented in this paper. Electrical performance of such interconnect innovation is discussed and pitted against the conventional PoP methods using solder ball connection, as well as the recent developed over-molded interconnection technology. The advantages of the aforementioned silicon and package interposer technology from electrical performance perspective such as signal integrity in terms of impedance matching, noise shielding, electrical return and insertion losses are presented based on 3D passive modeling and simulation data. Device input-output (IO) density and physical scalability as associated with the above inter-package connection systems are also being analyzed and further elaborated. Transient analysis in terms of impulse response and TDR are presented in this paper as well.

Published in:

Quality Electronic Design (ASQED), 2011 3rd Asia Symposium on

Date of Conference:

19-20 July 2011