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A wideband Low Noise Amplifier (LNA) is demonstrated by using the inductively degenerated LNA architecture. This wideband operates in range of 1.575 GHz to 2.48 GHz frequency band. The design of the LNA utilizes the Power Constraint Noise Optimization (PCNO) technique in determining the device size. The simulation results achieved the maximum power gain S21 at 13.7 dB to 10.3 dB, input reflection coefficient S11 at -7.2 dB to -9.5 dB, output reflection coefficient S22 at -17 dB to -10 dB, reverse isolation S12 at -54.4 dB to -52.1 dB and noise figure (NF) at 2.31 dB to 3.12 dB in the frequency range. Linearity result is based on the Input Third-Order Intercept Point (IIP3) is -5.48 dBm. The design draws and obtained at low total power consumption at 14.4 mW and all results met specification. The design was implemented in 0.18 μm CMOS technology. The performances obtained are from the LNA with on-chip matching circuitries.