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Design and Fabrication of 4H–SiC Lateral High-Voltage Devices on a Semi-Insulating Substrate

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7 Author(s)
Wen-Shan Lee ; Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Kuan-Wei Chu ; Chih-Fang Huang ; Lurng-Shehng Lee
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Design and fabrication of 4H-SiC lateral high-voltage devices on semi-insulating substrates based on the charge compensation principle have been investigated in this work. In the simulation, field plates are critical in relieving the electric field crowding at junction corners at high reverse biases. By incorporating field plates with proper lengths, the breakdown voltage (BV) of a single-zone reduced-surface-field (RESURF) device with a 100- μm drift region can be improved from 3360 to 5880 V. The BV can be further enhanced to 8000 V by using a two-zone RESURF structure. The reduction in BV by 10% charge imbalance variation is also improved from 49% for a single-zone structure to 36% for a two-zone structure. Simulation also shows that oxide charges and other surface charges will offset the optimized charge imbalance conditions and, therefore, should be considered in design if the amount is significant. A 4H-SiC JFET with a two-zone RESURF region was fabricated to demonstrate the advantages of lateral devices based on these concepts. The fabricated lateral 4H-SiC JFET has a BV of 4200 V and a specific on -resistance of 454 mΩ·cm2. The figure of merit is as high as 38.8 MW/cm2.

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Electron Devices, IEEE Transactions on  (Volume:59 ,  Issue: 3 )