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Browse Journals & Magazines > Computers, IEEE Transactions ...> Volume:39 Issue:12 Help

Fault detection and design complexity in C-testable VLSI arrays

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2 Author(s)
Lombardi, F. ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Huang, W.-K.

An extension of a previous approach to fault detection and C -testability of orthogonal iterative arrays is presented. The state transition table of a basic cell is analyzed. Five new states are added to it. It is proved that even though the number of additional states in the proposed approach is greater than previous approaches, (five states compared to four), the required number of test vectors is considerably reduced (by a factor of approximately 4/9). An approach to implement the proposed C-testability approach into logic design is also presented. Complexity of this implementation is analyzed

Published in:
Computers, IEEE Transactions on  (Volume:39 ,  Issue: 12 )

Date of Publication: Dec 1990

Page(s):
1477 - 1481
ISSN :
0018-9340
INSPEC Accession Number:
3847684
Digital Object Identifier :
10.1109/12.61070
Product Type:
Journals & Magazines
Date of Current Version :
06 August 2002
Issue Date :
Dec 1990
Sponsored by :
IEEE Computer Society

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