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An upper bound on expected clock skew in synchronous systems

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2 Author(s)
S. D. Kugelmass ; Dept. of Comput. Sci., Princeton Univ., NJ, USA ; K. Steighlitz

A statistical model is considered for clock skew in which the propagation delays on every source-to-processor path are sums of independent contributions, and are identically distributed. Upper bounds are derived for expected skew, and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two special cases of clock distribution. In the first, the metric-free model, the total delay in each buffer stage is Gaussian with a variance independent of stage number. In this case, the upper bound on skew grows as Θ (log N). The second, metric, model, is meant to reflect VLSI constraints. Here, the clock delay in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. In this case, the upper bound on expected skew is Θ (N 1/4 (log N)1/2)

Published in:

IEEE Transactions on Computers  (Volume:39 ,  Issue: 12 )