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Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010

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2 Author(s)
Gort, M. ; Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada ; Anderson, J.H.

We present parallelization and heuristic techniques to reduce the run-time of field-programmable gate array (FPGA) negotiated congestion routing. Two heuristic optimizations provide over 3× speedup versus a sequential baseline. In our parallel approach, sets of design signals are assigned to different processor cores and routed concurrently. Communication between cores is through the message passing interface communications protocol. We propose a geographic partitioning of signals into independent sets to help minimize the communication overhead. Our parallel implementation provides approximately 2.3× speedup using four cores and produces deterministic/repeatable results. When combined, the parallel and heuristic techniques provide over 7× speedup with four cores versus the router in the widely used Versatile Place and Route (VPR) FPGA placement/routing framework, with no significant impact on circuit speed or wirelength.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:31 ,  Issue: 1 )

Date of Publication:

Jan. 2012

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