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Modular architecture for high performance implementation of the FRR algorithm

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2 Author(s)
Sapiecha, K. ; Dept. of Electr. Eng., Tech. Univ. of Kielce, Poland ; Jarocki, R.

A novel VLSI-oriented architecture to compute the discrete Fourier transform is presented. It consists of a homogeneous structure of processing elements. The structure has a performance equal to 1/t transforms per second, where t is the time needed for the execution of a single butterfly computation or the time needed for the collection of a complete vector of samples, whichever is longer. Although the system is not optimal (it achieves O(N 3 log4 N) area×time2 performance), the architecture is modular and makes it possible to design a system which performs FFT of any size without any extra circuitry. Moreover, the system can provide a built-in self-test and self-restructuring. The modular system is easy to integrate. Processing elements (PEs) are connected to the neighboring PEs only, and form a linear network easy to implement in two and three dimensions. The number of pins required for a chip does not depend on the number of PEs integrated on it, nor on the size of the transform. The system consists of only one type of integrated circuit with a structure irrespective of the transform size, which considerably reduces the cost of implementation

Published in:

Computers, IEEE Transactions on  (Volume:39 ,  Issue: 12 )

Date of Publication:

Dec 1990

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