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Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC

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5 Author(s)
Moongon Jung ; Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA ; Xi Liu ; Sitaraman, S.K. ; Pan, D.Z.
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In this work, we propose an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design optimization methodology to alleviate TSV interfacial crack problems in 3D ICs. First, we analyze TSV interfacial crack at TSV/dielectric liner interface caused by TSV-induced thermo-mechanical stress. Then, we explore the impact of TSV placement in conjunction with various associated structures such as landing pad and dielectric liner on TSV interfacial crack. Next, we present a full-chip TSV interfacial crack analysis methodology based on design of experiments (DOE) and response surface method (RSM). Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.

Published in:

Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on

Date of Conference:

7-10 Nov. 2011

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