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High-level synthesis with distributed controller for fast timing closure

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2 Author(s)
Seokhyun Lee ; Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea ; Kiyoung Choi

Centralized controllers commonly used in high-level synthesis often cause long wires and high load capacitance and that is why critical paths typically occur on paths from controllers to data registers. However, conventional high level synthesis has focused on the delay of datapaths making it difficult to solve the timing closure problem during physical synthesis. This paper presents a hardware architecture with a distributed controller, which makes the timing closure problem much easier. It also presents a novel high-level synthesis flow for synthesizing such hardware through datapath partitioning and controller optimization. According to our experimental results, the proposed approach reduces the controller and interconnect delay by 20.3-27.4% and the entire critical path delay by 6.6~10.3% with 0.2~13.3% area overhead. Even without area overhead, it reduces the critical path delay by 5.8~10%.

Published in:

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Date of Conference:

7-10 Nov. 2011