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Route-Aware Task Mapping Method for Fault-Tolerant 2D-Mesh Network-on-Chips

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5 Author(s)
Kutami, H. ; Fac. of Sci. & Technol., Sophia Univ., Tokyo, Japan ; Fukushima, Y. ; Fukushi, M. ; Yairi, I.E.
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This paper deals with the issue of task mapping onto fault-tolerant 2D-Mesh Network-on-Chips (2D-MNoCs). In the fault-tolerant 2D-MNoCs, fault-tolerant deadlock-free routing control without assistance of hardware (such as lookup table and virtual channel) is desirable due to simple router architecture, low power consumption and easy fault diagnosis. For such fault-tolerant 2D-MNoCs, existing task mapping methods are not efficient because task assignment process and route decision process, which are closely interdependent, are performed separately. In this paper, we propose a new route-aware task mapping method based on a generic algorithm. Our method considers the effect of overlapped routing paths provided by a fault-tolerant routing control in assigning tasks to nodes and obtains a quasi-optimal solution by the genetic algorithm. Experimental study compares overall performances of our method with a random mapping method under the random and cluster fault models, and shows that our method consistently leads to reduction in the total execution time of mapped applications.

Published in:

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on

Date of Conference:

3-5 Oct. 2011

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