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A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

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4 Author(s)
Yung Sern Tan ; IC Design Centre, Nanyang Technol. Univ., Singapore, Singapore ; Kiat Seng Yeo ; Chirn Chye Boon ; Manh Anh Do

This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18- μm CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 6 )