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Polysilicon Spacer Gate Technique to Reduce Gate Charge of a Trench Power MOSFET

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2 Author(s)
Raghvendra Sahai Saxena ; Solid State Physics Laboratory, Delhi, India ; M. Jagadesh Kumar

We propose a new trench gate power MOSFET with poly-Si spacers formed in the trench to work as gate material. This approach reduces the total gate charge and gate-to-drain capacitive coupling without affecting any other device performance parameter. Using 2-D numerical simulation on a ~25-V trench gate MOSFET, we have shown that using a 50-nm-wide spacer gate in a 1×1 μm trench may give >; 40% reduction in the gate-to-drain charge compared with the conventional device. The proposed technique has been shown to be better than the other techniques proposed earlier for reducing gate charge as it does not affect the gate control of the accumulation region charge or any other performance parameter, e.g., breakdown voltage, and can be implemented along with any of the existing techniques.

Published in:

IEEE Transactions on Electron Devices  (Volume:59 ,  Issue: 3 )