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Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors

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3 Author(s)
Yang Li ; Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA ; Melhem, R. ; Jones, A.K.

Traversing page table during virtual to physical address translation causes significant pipeline stalls when misses occur in the translation-lookaside buffer (TLB). To mitigate this penalty, we propose a fast, scalable, multi-level TLB organization that leverages page sharing behaviors and performs efficient TLB entry placement. Our proposed partial sharing TLB (PSTLB) reduces TLB misses by around 60%. PSTLB also improves TLB performance by nearly 40% compared to traditional private TLBs and 17% over the state of the art scalable TLB proposal.

Published in:

Computer Architecture Letters  (Volume:11 ,  Issue: 2 )