By Topic

A High Speed Parallel Timing Recovery Algorithm and Its FPGA Implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Changxing Lin ; Dept. of Eng. Phys., Tsinghua Univ., Beijing, China ; Jian Zhang ; Beibei Shao

The paper presents an efficient and parallel symbol timing recovery algorithm suitable for very high speed demodulator and easy to implement on FPGA platform. The proposed timing recovery algorithm has a dual feedback structure which makes up of frequency domain timing phase correction, first reported in Alternate Parallel Receiver (APRX), and parallel FIFOs based delete-keep algorithm. In the timing error detector, we adopt the O\&M algorithm. We also investigate their high speed parallel implementation structures suitable for FPGA platform. The fixed point simulation shows that our proposed algorithm can work efficiently with performance loss less than 0.5dB. Besides, the algorithm is implemented with a Xilinx XC6VLX240T FPGA chip, and reaches the maximum running frequency of 188 MHz. Thus, it sustains a symbol rate of 1.5 Gsps when 4 samples per symbol are employed.

Published in:

Intelligence Information Processing and Trusted Computing (IPTC), 2011 2nd International Symposium on

Date of Conference:

22-23 Oct. 2011