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Two architectures of 77-GHz fractional-N phase-locked loops (PLLs) for FMCW radars are presented. Both architectures show good performance in terms of phase noise with -79 dBc/Hz at 100 kHz offset frequency. To achieve this, the integration of a delay-locked loop-based frequency multiplier for the reference signal in the PLL is proposed. It exhibits very low phase noise and proves to be an excellent alternative to other types of multipliers for lower frequencies.
Published in:
Microwave Integrated Circuits Conference (EuMIC), 2011 European
Date of Conference: 10-11 Oct. 2011
- Page(s):
- 196 - 199
- Print ISBN:
- 978-1-61284-236-3
- INSPEC Accession Number:
- 12437240
- Conference Location :
- Manchester
- Product Type:
- Conference Publications
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