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In this paper, we model and analyse a hierarchical TSV-based chip-package co-design of the power delivery network (PDN) for three-dimensional integrated circuits (3DICs). It is a significant design consideration to combine chip/package PDN structures, accurately characterize and quantify their overall impedance,1st-droop effect and resonant noise behaviour for multi-stacked chips. To better understand how to reduce noise, particularly simultaneous switching noise (SSN) and determine voltage drop impact on power delivery networks for 3DICs, an analytical model is enhanced and applied to estimate the different noise levels of hierarchical TSV-based PDN structures. The on-chip parasitic capacitances and intentionally added decoupling capacitors help counter any Ldi/dt variations from the power supply rails as a result of the inductive effects in TSVs. With technology interest in embedded applications, the hierarchical chip-package TSV-based PDN design is modeled after a multi- stacked memory subsystem, a silicon interposer and package structure. A segmentation-based method is used to calculate the overall impedance of the hierarchical PDN system. An analytical expression is modified and used to quantify the transient response characteristics of 1st-droop and resonant noise property.