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Decoupling capacitor stacked chip (DCSC) in TSV-based 3D-ICs

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5 Author(s)
Eunseok Song ; Dept. of Electr. Eng., KAIST, Daejeon, South Korea ; Kyoungchoul Koo ; Myunghoi Kim ; Jun So Pak
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In this paper, we introduce a new decoupling capacitor stacked chip (DCSC) with discrete capacitors and through-silicon-vias (TSVs) that can overcome the limitations of the conventional decoupling capacitor solutions such as expensive on-chip NMOS capacitor and package-level discrete decoupling capacitor with narrow-band. The key idea of the proposed TSV-based DCSC is mounting the decoupling capacitors such as silicon-based NMOS capacitor and discrete capacitor on the backside of a chip and connecting the capacitors to the on-chip PDN through TSVs. Therefore, the TSV-based DCSC provides the lowest parasitic inductance (ESL: under several tens pH) through a short interconnections between the on-chip PDN and decoupling capacitors as well as the largest capacitance (up to several uF) by stacking the additional decoupling capacitors to 3D-IC systems.

Published in:

Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on

Date of Conference:

23-26 Oct. 2011