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To sustain the pace of integration density improvement, 3-D IC technology is hailed as a “Beyond Moore” driver. It has been demonstrated to have great potential to diminish footprint, reduce interconnect delay, promote system performance, decrease power consumption and facilitate integration of heterogeneous processes. Besides, it is commonly cited as a means of reducing lateral wirelength. Some early theoretical and experimental studies have also shown that 3-D IC can significantly reduce lateral wirelength. However, the effect of through-silicon via (TSV) area overhead on the wirelength has been largely overlooked. In this paper, we derive a mathematical upper bound on the wirelength benefit of placing a circuit in 3-D that takes the TSV area overhead into account. For a set of IBM placement benchmarks scaled to the 32 nm process, we show that 3-D integration cannot help to reduce the wirelength under current TSV technologies.