A Hierarchical Self-Repairing Architecture for Fast Fault Recovery of Digital Systems Inspired From Paralogous Gene Regulatory Circuits

Self-repairing digital systems have received increasing attention as modern systems are getting more complex and fast. Currently available self-repairing architectures have, however, some limitations such as storage overhead required to prepare all possible rewiring strategies and temporal incorrectness caused by elongated repairing time. In this paper, we propose a novel self-repairing architecture for fast fault recovery with an efficient use of limited resources, which can be easily applied to real complex digital systems. The proposed architecture consists of three layers: a working layer, a control layer, and an interface layer. The working layer employs a hybrid scheme of using both redundant and empty cells with a newly devised self-test. This relieves the overhead of redundant cells required to be prepared in advance by considering every possible fault situation. In the control layer, an ordered assignment control is proposed. The order of working-priority of each processor that controls a normal cell in the working layer is predetermined. A faulty processor is detected by a majority decision among neighboring control processors and corrected by rearranging the order of working-priority. The interface layer connects an external PC for reprogramming. Through this fault recovery mechanism, the system can keep normal functioning under noisy environments. We implemented the proposed self-repairing architecture using an field-programmable gate array board with an application of a dot-matrix LED display and verified its robust operation. The proposed architecture can be widely used as a new platform for self-repairing systems.