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Design, analysis, and evaluation of concurrent checking sorting networks

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2 Author(s)
Kantawala, K. ; Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA ; Tao, D.L.

In this brief, we propose two new concurrent error-detection (CED) schemes for a class of sorting networks, e.g., odd-even transposition, bitonic, and perfect shuffle sorting networks. A probabilistic method is developed to analyze the fault coverage, and the hardware overhead is evaluated. We first propose a CED scheme by which all errors caused by single faults in a concurrent checking sorting network can be detected. This scheme is the first one available to use significantly less hardware overhead than duplication without compromising throughput. From this scheme, we develop another fault detection scheme which sharply reduces the hardware overhead (using an additional 10%/spl sim/30% hardware) but still achieves virtually 1001 fault coverage.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:5 ,  Issue: 3 )

Date of Publication:

Sept. 1997

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