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A reconfigurable VLSI coprocessing system for the block matching algorithm

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2 Author(s)
Bugeja, A. ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Woodward Yang

Several VLSI architectures for the full-search block matching algorithm have been proposed in recent years due to its computation and I/O-intensive nature and its importance in various computer vision and image processing applications. This paper presents a new coarse grained reconfigurable coprocessor which is suitable for integration with general purpose microprocessors. The 180000 transistor custom VLSI design was implemented in 0.6 /spl mu/m CMOS on a 4.12 min/spl times/2.59 mm die and has been fully tested up to 33 MHz. For a typical image database search application, a sample system consisting of four coprocessors interfaced through a 33 MHz PCI bus will provide a speedup of 320/spl times/ over an 80486 DX2/66 MHz and 64/spl times/ over a 150-MHz Pentium running fully optimized assembly code.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:5 ,  Issue: 3 )