By Topic

Effects of simultaneous switching noise on the tapered buffer design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Vemuru, Srinivasa R ; Dept. of Electr. Eng., City Univ. of New York, NY, USA

Complementary metal-oxide-semiconductor (CMOS) output buffers, comprised of a series of tapered inverters, are used to drive large off-chip capacitances. The ratio of the size of transistors between two consecutive stages is the buffer taper factor. With higher frequency of operation and simultaneous switching of the output drivers, the parasitic inductance present at the pin-pad-package interface results in significant switching noise on the power lines. A comprehensive analysis and estimate of simultaneous switching noise (SSN) including the velocity saturation effects seen in the submicron transistors during the switching of output drivers is presented. The effect of SSN on the overall buffer propagation delay and transition time is discussed. The presence of SSN results in an increase in the optimum taper factor between inverter stages for a given capacitive load. Beyond a critical value, the output transition time of a tapered buffer increases with reducing taper factor due to SSN. SSN can be reduced by skewing the switching of output buffers, SPICE simulation results show that skewing buffer switching with additional inverter stages reduces SSN and increases buffer propagation delay.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:5 ,  Issue: 3 )