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Vertically integrated silicon-germanium nanowire field-effect transistor

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6 Author(s)
Rosaz, G. ; Laboratoire des Technologies de la Microélectronique (LTM)–UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France ; Salem, B. ; Pauc, N. ; Potie, A.
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Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.3660244 

We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9 V, an ION/IOFF ratio of 104. The subthreshold slope was estimated to be around 0.9 V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps Dit ∼ 1.2 × 1013 cm-2 eV-1. Comparisons are made with both vertical Si and horizontal SiGe FETs performances.

Published in:

Applied Physics Letters  (Volume:99 ,  Issue: 19 )

Date of Publication:

Nov 2011

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