By Topic

Performance Enhancement of Silicon Nanowire Memory by Tunnel Oxynitride, Stacked Charge Trap Layer, and Mechanical Strain

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
C. J. Huang ; Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan ; C. H. Yang ; C. Y. Hsueh ; J. H. Lee
more authors

Heavily doped silicon nanowires (SiNWs) are adopted to fabricate a memory device composed of an AlON tunnel layer and a HfO2/HfAlO charge trap bilayer, which exhibits a large memory window of 4.6 V when operated in the program/erase phases, i.e., +12 V for 100 μs and -12 V for 10 ms, along with excellent 70% extrapolated ten-year data retention and good endurance up to 105 cycles. Strain effects on SiNW memory characteristics have also been investigated. It is demonstrated that the tensile strain increases the program window and the compressive strain improves the data retention. The underlying mechanism is attributed to the incorporation of nitrogen in the AlON tunnel layer.

Published in:

IEEE Electron Device Letters  (Volume:33 ,  Issue: 1 )