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A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction

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5 Author(s)
Surya S. Dan ; Nanoelectronic Devices Laboratory, EPFL, Lausanne, Switzerland ; Arnab Biswas ; Cyrille Le Royer ; Wladyslaw Grabinski
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There are several techniques for junction profiling available in literature, yet none of them are practically suitable for the accurate determination of the lateral junction steepness in TFET devices, which is the most important parameter influencing TFET performance. In this work, a simple physics-based compact analytical model has been developed for the junction steepness as a function of the doping concentration and the maximum electric field at the junction. Using the underlying physics, we report a novel yet simple method to estimate the lateral junction steepness using only the I-V measurements on a p+-i- n+ tunnel diode test structure fabricated on the same wafer as the TFET with common process steps. Assuming that doping concentration, Si thin-film thickness, and buried-oxide thickness are known from the fabrication process, this algorithm uses the maximum electric field extracted from the I-V measurements and applies the analytical model to estimate the junction steepness. It has been observed that the estimations based on this method have a maximum deviation of sub-0.2 nm/decade from the actual junction steepness of the investigated devices.

Published in:

IEEE Electron Device Letters  (Volume:33 ,  Issue: 2 )