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Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow

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4 Author(s)
Hui-Hsiang Tung ; Department of Computer Science and Engineering, Yuan Ze University, Chung-Li, Taiwan ; Rung-Bin Lin ; Mei-Chen Li ; Tsung-Han Heish

A structured application-specific integrated circuit (ASIC) has prefabricated yet configurable logic block arrays. We investigate some important via-configurable logic block (VCLB) design issues. We particularly focus on creating a VCLB layout that enables a standard cell like design. We propose the VCLB composability concept which enables us to use multiple VCLB instances to realize a complex logic gate. We devise four new VCLBs and construct several cell libraries based on these VCLBs. We develop a design flow mostly using industrial design tools and propose a method to evaluate VCLB viability. The experimental results show that a medium-grained VCLB that realizes a rich set of logic functions attains the best performance.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:20 ,  Issue: 12 )