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Chip-scale packaging

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1 Author(s)
Thompson, P. ; Semicond. Technol. Group, Motorola Inc., Tempe, AZ, USA

Uniting the advantages of bare die and mainstream packaging, these minimal IC supports are racing to the aid of portable yet powerful products. Rigorously defined, the perimeter of such a package is no more than 1.2 times the perimeter of the die it contains, so that few other IC packages are any smaller. This reduction in size is the key driver of the popularity of the approach. But because the term chip-scale has a marketing value, some manufacturers have extended it to cover other sizes, too. Chip-scale packaging technology is still taking its first steps into the marketplace, and issues of standards, design, and reliability remain to be solved. Even so, an infrastructure for the technology is beginning to develop, and its potential market seems to be guaranteed, not least by consumer thirst for portable electronic applications, for which the small, light package is a natural

Published in:

Spectrum, IEEE  (Volume:34 ,  Issue: 8 )

Date of Publication:

Aug 1997

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