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Over the last few decades, silicon-on-insulator (SOI) technology has been identified as one possible solution for enhancing the performance of CMOS because of its numerous advantages over conventional bulk CMOS technology. One of the primary drawbacks of short-channel SOI MOSFET is the degradation of device threshold voltage with decreasing channel length. Drain-induced barrier-lowering (DIBL) effect, generated from high drain bias, is the main cause behind this length-dependent nature of threshold voltage. This “instability” in threshold voltage is responsible for making SOI device design very challenging. The instability that is known as the threshold voltage rolloff restricts further scaling of SOI devices. In this paper, an idea of work function engineering with continuous horizontal mole fraction variation in a binary alloy gate has been proposed and implemented theoretically. Analytical model-based simulation verified that performance of proposed SOI MOSFET is improved as it has higher immunity to DIBL effect.