Parallel FFT implementation based on multi-core DSPs

The paper proposes a new implementation platform for parallel FFT called multi-core DSPs, which uses Serial RapidIO (SRIO) to achieve DSP-to-DSP communication and utilizes Enhanced Direct Memory Access (EDMA3) to realize core-to-core communication. The simulation results show this architecture not only effectively solves the bottleneck of system interconnection, but also greatly improves executing efficiency of Fast Fourier Transform (FFT). Especially for large FFT points, this advantage is more obviously presented.