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The research of an efficient digital channelized receiver based on parallel architecture

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3 Author(s)
Xinyi Liu ; School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu, China ; Haifeng Wang ; Youxin Lv

For the non-maximum decimation of filter bank channels application, a digital channelized receiver based on parallel architecture is proposed to improve the data throughput and real-time processing ability. The simulation results verify the feasibility and effectiveness of the architecture.

Published in:

Computational Problem-Solving (ICCP), 2011 International Conference on

Date of Conference:

21-23 Oct. 2011