Referenced Items are not available for this document.
Multi-level electronic integration of massively parallel computers leads to latency effects and I/O bottlenecks. A new implementation scheme using MCM-to-MCM free-space optical interconnects is discussed in terms of architecture enhancement, system modeling and technical challenges. Building blocks of an experimental demonstrator including zero-biased-VCSEL with hybridized microlenses are also presented.
Published in:
Massively Parallel Processing Using Optical Interconnections, 1997., Proceedings of the Fourth International Conference on
Date of Conference: 22-24 June 1997
- Page(s):
- 167 - 177
- Print ISBN:
- 0-8186-7975-1
- INSPEC Accession Number:
- 5644578
- Digital Object Identifier :
- 10.1109/MPPOI.1997.609185
- Product Type:
- Conference Publications
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