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Massively parallel neural signal processing: System-on-Chip design with FPGAs

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2 Author(s)
Balasubramanian, K. ; Neural Instrum. Lab., Temple Univ., Philadelphia, PA, USA ; Obeid, I.

This work discusses the architectural layout and performance results of a SoC design for parallel neural signal processing. Architectural framework for scalability and scalar reconfigurability are presented. Architectural requirements for massive parallelism in neural recordings are presented. Prototype architecture with dual processors and multi-level reconfigurable platform design is presented. Functional modules of the platform include real-time spike detector and sorter for several hundreds of neural channels. Performance of the platform for a 300 channel interface is also discussed.

Published in:

Engineering in Medicine and Biology Society, EMBC, 2011 Annual International Conference of the IEEE

Date of Conference:

Aug. 30 2011-Sept. 3 2011