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A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering

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7 Author(s)
Qian Xie ; Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan ; Qian He ; Xiao Peng ; Ying Cui
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This paper presents a high parallel macro block level layered LDPC decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes with various code rates and code lengths. LDPC codes defined in WiMAX standard with 6 code rates and 19 code lengths are chosen as the demonstration of this architecture. Based on the proposed dedicated matrix reordering strategy, this decoder costs 12-24 clock cycles per iteration for different code rates. Compared with the state-of-art work, this decoder reduces total memory bits to a great extent and achieves 2x-4.3x higher parallelism with 1.2x hardware cost. The synthesis result proves the low power potential of this architecture.

Published in:

Signal Processing Systems (SiPS), 2011 IEEE Workshop on

Date of Conference:

4-7 Oct. 2011

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