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In this paper, we present a low energy image processing system design based on efficient accuracy-energy tradeoffs. The proposed design allows aggressive voltage scaling in the presence of process variation by employing an error concealing method based on the inherent error tolerance of digital signal processing applications. Based on a system-level analysis, we demonstrate that significant energy savings can be achieved from voltage scaling and switching activity reduction for computational components. Using the proposed method, we can also achieve energy savings for other subsystems such as memory by increasing compression ratio. The experimental results show that average overall energy savings of up to ~50% are possible over a conventional design in a 45nm technology.
Signal Processing Systems (SiPS), 2011 IEEE Workshop on
Date of Conference: 4-7 Oct. 2011