By Topic

Low energy process variation tolerant digital image processing system design based on accuracy-energy tradeoffs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Se Hun Kim ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Mukhopadhyay, S. ; Honggab Kim ; Wolf, M.

In this paper, we present a low energy image processing system design based on efficient accuracy-energy tradeoffs. The proposed design allows aggressive voltage scaling in the presence of process variation by employing an error concealing method based on the inherent error tolerance of digital signal processing applications. Based on a system-level analysis, we demonstrate that significant energy savings can be achieved from voltage scaling and switching activity reduction for computational components. Using the proposed method, we can also achieve energy savings for other subsystems such as memory by increasing compression ratio. The experimental results show that average overall energy savings of up to ~50% are possible over a conventional design in a 45nm technology.

Published in:

Signal Processing Systems (SiPS), 2011 IEEE Workshop on

Date of Conference:

4-7 Oct. 2011