Skip to Main Content
Channel estimation based on superimposed training (ST) has been an active research topic around the world in recent years, because it offers similar performance when compared to methods based on pilot assisted transmissions (PAT), with the advantage of a better bandwidth utilization. However, physical implementations of such estimators are still under research, and only few approaches have been reported to date. This is due to the computational burden and complexity involved in the algorithms in conjunction with their relative novelty. In order to determine its suitability for commercial applications, counting with the performance and complexity analysis of the ST approaches is mandatory. This work proposes, at a first time, a full-hardware channel estimator architectures for an ST receiver and for one of its variants, known as data-dependent superimposed training (DDST). The architectures were described using Verilog HDL and implemented in Xilinx Virtex-5 XC5VLX110T FPGA. A fixed-point analysis has been carried out, allowing the design to produce practically equal performance to those achieved with the floating-point models. The synthesis results showed a reduced slices consumption (2%) and frequencies operation of 149 MHz, which allows to conclude that ST/DDST receivers can be utilized in practical developments.