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Architecture and design of a very fast real time delay insensitive asynchronous morphological processor in GaAs

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2 Author(s)
Montiel-Nelson, J.A. ; Centre for Appl. Microelectron., Campus Univ. de Tafira, Spain ; Nooshabai, S.

Delay insensitive asynchronous design techniques are employed to implement a mathematical morphology processor in GaAs. A modified version of the DCVSL family is introduced, in order to achieve ultra-fast data rates. Simulation of the architecture implementation in GaAs MESFET 0.6 μm Vitesse technology demonstrates the reliability of this ASIC system for high end image processing applications

Published in:

TENCON '96. Proceedings., 1996 IEEE TENCON. Digital Signal Processing Applications  (Volume:1 )

Date of Conference:

26-29 Nov 1996

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