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Low-power pulse-triggered flip-flop design using gated pull-up control scheme

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1 Author(s)
J. -F. Lin ; Department of Information and Communication Engineering, Chaoyang University of Technology, Taiwan

A new implicit type pulse triggered flip-flop design aimed at solving a common transistor stacking problem is presented. A pull-up transistor gating scheme is devised to avoid a bulky discharging path causing excessive power consumption. Via a bootstrap technique, the required gating pulse signal is obtained free from a modified delay inverter design. Circuit analyses and post-layout simulations are provided to prove the superiority of the design in terms of layout area and power-delay product.

Published in:

Electronics Letters  (Volume:47 ,  Issue: 24 )