By Topic

Low-power pulse-triggered flip-flop design using gated pull-up control scheme

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Lin, J.-F. ; Dept. of Inf. & Commun. Eng., Chaoyang Univ. of Technol., Taichung, Taiwan

A new implicit type pulse triggered flip-flop design aimed at solving a common transistor stacking problem is presented. A pull-up transistor gating scheme is devised to avoid a bulky discharging path causing excessive power consumption. Via a bootstrap technique, the required gating pulse signal is obtained free from a modified delay inverter design. Circuit analyses and post-layout simulations are provided to prove the superiority of the design in terms of layout area and power-delay product.

Published in:

Electronics Letters  (Volume:47 ,  Issue: 24 )