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A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta–Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation

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4 Author(s)
Chan-Hsiang Weng ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Chen-Chien Lin ; Yu-Cheng Chang ; Tsung-Hsien Lin

A second-order continuous-time delta-sigma modulator incorporating a proposed 4-bit asynchronous sequential quantizer and a digital excess-loop-delay (ELD) compensation technique is presented. The sequential operation of the proposed quantizer facilitates low power consumption while the hardware-efficient digital compensation technique allows the modulator to accommodate ELD. With a 1-MHz bandwidth and a 60-MHz sampling rate, the measured peak signal-to-noise-and-distortion ratio and dynamic range are 62 and 67 dB, respectively. Fabricated in a 90-nm CMOS, this chip consumes only 0.89 mW from a 1.2-V supply.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:58 ,  Issue: 12 )