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High Speed Architectures for Finding the First two Maximum/Minimum Values

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3 Author(s)
Luca G. Amaru ; Dipt. di Elettron., Politec. di Torino, Torino, Italy ; Maurizio Martina ; Guido Masera

High speed architectures for finding the first two maximum/minimum values are of paramount importance in several applications, including iterative (e.g., turbo and low-density-parity-check) decoders. In this brief, stemming from a previous work, based on radix-2 solutions, we propose higher and mixed radix implementations that improve the architecture latency. Post place and route results on a 180-nm CMOS standard cell technology show that the proposed architectures achieve lower latency than radix-2 solutions with a moderate area increase.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:20 ,  Issue: 12 )