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To guarantee that an application-specific integrated circuit (ASIC) meets its timing requirement, at-speed scan testing becomes an indispensable procedure for verifying the performance of ASIC. However, at-speed scan test suffers the test-induced yield loss. Because the switching-activity in test mode is much higher than that in normal mode, the switching-induced large current drawn causes severe IR drop and increases gate delay. X-filling is the most commonly used technique to reduce IR-drop effect during at-speed test. However, the effectiveness of X-filling depends on the number and the characteristic of X-bit distribution. In this paper, we propose a physical-location-aware X-identification which redistributes X-bits so that the maximum switching-activity is guaranteed to be reduced after X-filling. We estimate IR-drop using RedHawk tool and the experimental results on ITC'99 show that our method has an average of 9.42% more reduction of maximum IR-drop as compared to a previous work which redistributes X-bits evenly in all test vectors.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:20 , Issue: 12 )
Date of Publication: Dec. 2012