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Concept and design of exhaustive-parallel search algorithm for Network-on-Chip

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7 Author(s)
Deivasigamani, M. ; Dept. of Electron. Eng., Anna Univ., Chennai, India ; Tabatabaei, S. ; Mustafa, N. ; Ijaz, H.
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This paper presents the concept and design of exhaustive-parallel search algorithm for Network-on-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 8×8 mesh architecture and its performance is evaluated.

Published in:

SOC Conference (SOCC), 2011 IEEE International

Date of Conference:

26-28 Sept. 2011

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