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VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes

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4 Author(s)
Ming-Der Shieh ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Shih-Hao Fang ; Shing-Chung Tang ; Der-Wei Yang

This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.

Published in:

SOC Conference (SOCC), 2011 IEEE International

Date of Conference:

26-28 Sept. 2011