Skip to Main Content
The Synchronous Transfer Architecture is a low power architecture of VLIW processor, which enables the direct data routing through buffered output ports of functional units. To improve the system efficiency of STA, in this paper we propose a novel approach to integrate compiler techniques with architecture exploration: A fuzzy control system is implemented to help the compiler back-end determine the optimal configuration of the STA processor and the corresponding target VLIW for different applications. This approach achieves the integration of the optimizations of code generation and hardware design. According to our studies, the drop in execution time is between 18% and 43% compared to the compiled ARM assembly code. Up to 42.4% register read and 67.9% register write operations are cut down on average. Except for reding the input data and writing back the results, all the other memory accesses for ARM architecture are avoided, giving us a dramatic reduction in the power consumption. Finally, the novel approach enjoys short compilation time and less complex implementation.
SOC Conference (SOCC), 2011 IEEE International
Date of Conference: 26-28 Sept. 2011