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A merged adder/D-type flip-flop (DFF) is presented by using the back-gate feedback technique. By using this merged adder/DFF, a slicerless one-tap decision feedback equalizer (DFE) and a cascaded DFE are fabricated in 65-nm CMOS technology. For a cable loss of 12 dB and a 30-Gb/s pseudorandom bit sequence (PRBS) of 27 - 1, the measured bit error rate of the slicerless one-tap DFE is below 10-11. Its power dissipation is 27 mW from a 1-V supply. For a cable loss of 12 dB and a 30-Gb/s PRBS of 215 - 1, the measured bit error rate of the cascaded DFE is below 10-12. This cascaded DFE consumes 55 mW from a 1-V supply.