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Circuit-Level Layout-Aware Single-Event Sensitive-Area Analysis of 40-nm Bulk CMOS Flip-Flops Using Compact Modeling

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9 Author(s)
Kauppila, J.S. ; Inst. for Space & Defense Electron. (ISDE), Vanderbilt Univ., Nashville, TN, USA ; Haeffner, T.D. ; Ball, D.R. ; Kauppila, A.V.
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A circuit-level layout-aware single-event simulation capability is presented. Multiple 40-nm bulk CMOS flip-flops are analyzed to determine single-event upset (SEU) sensitive area. Comparisons between simulation results and broadbeam heavy-ion test data show excellent agreement. Simulations of single-event strikes over the entire flip-flop layout can be performed in less than 1 h.

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Nuclear Science, IEEE Transactions on  (Volume:58 ,  Issue: 6 )