Referenced Items are not available for this document.
A circuit-level layout-aware single-event simulation capability is presented. Multiple 40-nm bulk CMOS flip-flops are analyzed to determine single-event upset (SEU) sensitive area. Comparisons between simulation results and broadbeam heavy-ion test data show excellent agreement. Simulations of single-event strikes over the entire flip-flop layout can be performed in less than 1 h.
Published in:
Nuclear Science, IEEE Transactions on
(Volume:58
,
Issue:
6
)
Date of Publication: Dec. 2011
- Page(s):
- 2680 - 2686
- ISSN :
- 0018-9499
- INSPEC Accession Number:
- 12408902
- Digital Object Identifier :
- 10.1109/TNS.2011.2172692
- Date of Publication :
- 18 November 2011
- Date of Current Version :
- 12 December 2011
- Issue Date :
- Dec. 2011
- Sponsored by :
- IEEE Nuclear and Plasma Sciences Society
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