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Single-Event Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs

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9 Author(s)
Chatterjee, I. ; Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA ; Narasimham, B. ; Mahatme, N.N. ; Bhuva, B.L.
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CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the ion-induced single-event response between these two technology options, however, are not well understood. This paper presents a comparative analysis of heavy ion-induced upsets in dual-well and triple-well 40-nm CMOS SRAMs. Primary factors affecting the charge-collection mechanisms for a wide range of particle energies are investigated, showing that triple-well technologies are more vulnerable to low-LET particles, while dual-well technologies are more vulnerable to high-LET particles. For the triple-well technology, charge confinement and multiple-transistor charge collection triggers the “Single Event Upset Reversal” mechanism that reduces sensitivity at higher LETs.

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Nuclear Science, IEEE Transactions on  (Volume:58 ,  Issue: 6 )