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A new implementation of the post-stage tasks of motion estimation timation using SIMD architecture

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7 Author(s)
Zhang, Wujian ; Institute of Microelectronics, Tsinghua University, Beijing 100084, China ; Qiu, Xiaohai ; Zhou, Runde ; Chen, Hongyi
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Usually a single MPEG2 video ercoder chip realizes the multiple post-stage tasks of motion estimation, such as motion vector refinement and prediction error generation, using multiple hardware modules. This paper proposes a new architecture using only a single module to implement the post-stage tasks of motion estimation, which has a single instruction stream over multiple data streams (SIMD). The new architecture is simple and more regular; capable of providing sufficient computational power and of adapting to the encoding flexibility required by the MPEG2 standard. Therefore, it is a more suitable architecture for the system on a chip. NEL Corporation (NTT Electronics, Japan) has integrated a circuit based on this architecture into the single MPEG2 MP@ML encoder chip, which uses the multiresolution telescopic search motion estimation algorithm. Using 0.25μm CMOS, four-metal layer technology, this circuit has 15.4 M gates with an area of about 29 mm2. The operating clock frequency is 81 MHz.

Published in:

Tsinghua Science and Technology  (Volume:6 ,  Issue: 4 )

Date of Publication:

Oct. 2001

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