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Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory

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11 Author(s)
Won Bo Shim ; Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Seongjae Cho ; Jung Hoon Lee ; Dong Hua Li
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A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F2 size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:11 ,  Issue: 2 )

Date of Publication:

March 2012

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