Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory

A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F
$^2$
size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.