Referenced Items are not available for this document.
To fulfill high-speed and low-power specifications for both logic and analog applications, III-V FETs with high-κ gate dielectric stack are especially appealing, in particular for their ability to operate under low power supply voltage. Using complementary tools such as a 2D Poisson-Schrödinger solver and a Monte Carlo device simulator, we assess the potentiality of several III-V MOSFET structures in terms of gate charge control, static/dynamic performance and noise.
Published in:
SOI Conference (SOI), 2011 IEEE International
Date of Conference: 3-6 Oct. 2011
- Page(s):
- 1 - 2
- ISSN :
- 1078-621X
- E-ISBN :
- 978-1-61284-759-7
- Print ISBN:
- 978-1-61284-761-0
- INSPEC Accession Number:
- 12377558
- Conference Location :
- Tempe, AZ
- Digital Object Identifier :
- 10.1109/SOI.2011.6081701
- Product Type:
- Conference Publications
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