Assessment of III–V MOSFET architectures for low power applications using static and dynamic numerical simulation

To fulfill high-speed and low-power specifications for both logic and analog applications, III–V FETs with high-κ gate dielectric stack are especially appealing, in particular for their ability to operate under low power supply voltage. Using complementary tools such as a 2D Poisson-Schrödinger solver and a Monte Carlo device simulator, we assess the potentiality of several III–V MOSFET structures in terms of gate charge control, static/dynamic performance and noise.